DDR Configuration
Create a Vivado Project
Open Vivado and click Create Project.
Select a project name and path, then click Next.
Select RTL Project (check Do not specify sources at this time), then click Next.
Select the correct FPGA model (e.g., xc7z020clg400-2), then click Next → Finish.
Add the Zynq Processing System IP
In the Flow Navigator, click Create Block Design.
On the Block Design canvas, click the “+” button to add an IP, search for “Zynq”, select Zynq7 Processing System, and double-click to add it.
Click Run Block Automation (this automatically connects the PS-PL interface; the default settings can be kept).
Configure the DDR Controller
In the Block Design, double-click the Zynq IP to open the configuration interface.
Switch to the DDR Configuration tab:
DDR Controller Configuration
Memory Type: Select DDR3(Low). This choice should be based on the schematic. The main difference between DDR3 and DDR3(Low) is the operating voltage: DDR3 is 1.5V, while DDR3(Low) is 1.35V.
Memory Part: According to the datasheet, the chip model we are using is MT41K256M16TW-107, so the default selection is typically MT41K256M16 RE-125. Some subsequent parameters will be provided directly. To help understand how to configure each parameter, we will select Custom here.
Effective DRAM Bus Width: Since the core board has two DDR3 chips, and each DDR3 is 16-bit, the total data bus width is 32 bits. The rest of the settings can be left at their defaults.
Memory Part Configuration
The specific configuration is as follows:
The relevant parameters should be filled in by consulting the datasheet:
DRAM IC Bus Width: The data bus of the MT41K256M16TW-107 is 16 bits, and its capacity is 4096Mb, which is 512MB.
Speed Bin: Select DDR3 1600K here.
According to the MT41K256M16TW-107 Datasheet, the speed grade -107 corresponds to a data rate of 1866 and is backward compatible with 1600. When operating at 1600, its tRCD-tRP-CL parameters are 11-11-11.
According to the DDR3 SDRAM - Wikipedia page, when the tRCD-tRP-CL parameters are 11-11-11, the corresponding type is K.
Bank Address Count, Row Address Count, Col Address Count: These values can be found on page 15 of the datasheet:
CAS Latency(CL), tRCD, tRP: These can be obtained directly from the datasheet:
CAS Write Latency(CWL): Find the value in Table 55 of the datasheet:
tRC, tRASmin: Find the values in Table 55 of the datasheet:
tFAW: Find the value by consulting Table 2 and Table 58 in the datasheet:
Training/Board Details
First, check all the DRAM Training options:
There are two ways to fill in the remaining two sections: User Input and system calculates automatically.
User Input
If you need to calculate them manually, first select the automatic mode to note down the package delay (because the package delay is the signal transmission delay inside the chip package, which is not visible in Vivado), and then perform the manual calculation:
The formula for DQS to Clock Delay (ns) is as follows:
Where:
Path DelayCLK0 = Total delay of CLK0 (ps)
Path DelayDQS = Total delay of DQS (ps)
Dividing by 1000 converts picoseconds (ps) to nanoseconds (ns).
Formula Verification:
a. Calculate the path delay for CLK0
b. Calculate the path delay for DQS0
c. Calculate the DQS0 to Clock Delay
d. Calculation for other DQS signals
Similarly, for signals like DQS1, DQS2, etc., simply replace the corresponding L and
values and repeat the steps above.
The formula for Board Delay (ns) is as follows:
Where:
Path DelayCLK0 = Total delay of CLK0 (ps)
Path DelayDQ = Total delay of DQ (ps)
Dividing by 1000 converts picoseconds (ps) to nanoseconds (ns).
Formula Verification:
a. First, calculate the path delay for CLK:
Using CLK0 as an example:
Convert the length (in mm) to inches:
Calculate the path delay for CLK:
b. Then, calculate the path delay for (DQ[0:7]) (using (DQ7:0) as an example):
Convert the length (L_{DQ7:0}) (in mm) to inches:
Calculate the path delay for (DQ[0:7]):
c. Calculate (Board\ Delay) using the formula:
system calculates automatically
Calculated: The system calculates automatically. We obtain the lengths of the DDR net traces from PCB design software (like Altium Designer, Cadence, etc.), enter them into the Length column, and Vivado will automatically calculate the delay time. The interface is as follows:
Since we have two DDR3 chips, there are two pairs of differential clock signals. CLK0, CLK1, DQS0, and DQS1 are the signals for the first DDR3 chip, where CLK0/CLK1 provide the clock and DQS0/DQS1 control the 16-bit data bus. The same applies to the second DDR3 chip.
Enable Advanced options
This section can be left at its default settings.
Run the Application in Vitis
Select the template specifically for testing DDR:
Compile and run the project:
Display of run results:
Explanation of Results:
First, an explanation of the "eye diagram":
A DDR eye diagram is a graph formed by overlaying the waveforms of multiple data bits, as observed on an oscilloscope for high-speed serial signals. It is named for its resemblance to an "eye." It is a key tool for evaluating the signal integrity of DDR (Double Data Rate) memory.
Key Parameters
Ideal bit width: 128 units
Eye Min - Max (EYE_MIN - MAX): [8,108], [12,108], [12,100], [16,104]
Eye Center (EYE CENTER): 58/128, 60/128, 56/128, 60/128
Eye Width (EYE WIDTH): 78.12%, 75.00%, 68.75%, 67.50%
Eye Adjusted (EYE ADJUSTED): No specific data shown
bAnalysis
Eye Width: The eye width percentage indicates the stability of the signal. A higher percentage means the signal is more stable on that channel.
Eye Center: The eye center value shows the signal's position on the time axis. Ideally, the eye center should be close to 50% (64/128).
Eye Min - Max: This range shows the fluctuation of the signal on the time axis. A smaller range (like [8,108]) indicates less fluctuation for the signal on that channel (Lane - 0).